A nonvolatile memory is a semiconductor device that holds a stored data even if the semiconductor device is powered off, and is being widely used. Flash memory is one type of typical nonvolatile memories. The flash memory has a structure in which a transistor structuring a memory cell has a charge accumulation layer composed of a floating gate or an insulating membrane. A flash memory having a SONOS (Silicon Oxide Nitride Oxide Silicon) type structure is one of flash memories having the insulating layer acting as the charge accumulation layer, and stores data by accumulating a charge in a trap of a SiN (Silicon Nitride) membrane. U.S. Pat. No. 6,011,725 discloses a conventional flash memory that has a virtual ground type memory cell switching a source and a drain and operating them symmetrically as one of SONOS type of flash memories. With this structure, it is possible to form two charge accumulation regions in one charge accumulation layer of a transistor. And the memory cell is miniaturized because a bit line acts as a source and a drain and is built in a semiconductor substrate.
However, as the channel length shortens it is difficult to separate the two charge accumulation regions formed in the one charge accumulation layer, when the memory cell is miniaturized in a conventional flash memory. Japanese Patent Application Publication No. 2005-517301 discloses a conventional flash memory that solves this problem and has a miniaturized memory cell. FIG. 1 illustrates a cross sectional view of this conventional flash memory. As shown in FIG. 1, a groove 15 is formed on a semiconductor substrate 10. A bit line 12 is formed on the both sides of the groove 15 in the semiconductor substrate 10 and acts as a source and a drain. An ONO layer 23 composed of a bottom insulating membrane 14, a charge accumulation layer 16 and a top insulating membrane 18 is formed on a side surface of the groove 15. A word line 20 is formed on a side surface of the top insulating membrane 18 and acts as a gate electrode. Also, a channel length 17 is a circumference of the groove 15 as shown in FIG. 1, even if an interval between each of the bit lines is reduced. It is therefore possible to keep the channel length long and it is possible to separately form the two charge accumulation regions between the source and the drain.
However, in this conventional flash memory, a junction between the semiconductor substrate 10 acting as a P-type region and the bit line 12 acting as a N-type region is a PN junction 11 (shown in FIG. 1) where a dopant concentration changes gradually. This is because the bit line 12 is formed by implanting ions of dopant into the top surface of the semiconductor substrate 10 and the dopant concentration is low in the lower layer of the bit line 12. A data is written when an electron is implanted into the charge accumulation layer with a hot electron effect. The data is deleted when a hole is implanted into the charge accumulation layer with a hot hole effect. The electron and the hole are implanted into the charge accumulation layer near the PN junction 11 where the concentration of the dopant changes gradually. An energy of the electron and the hole is small because an electrical field is small at the PN junction 11 where the concentration changes gradually. It is therefore difficult to implant the electron and the hole into the charge accumulation layer. And there is a problem that the writing property or the deleting property of the data is degraded compared to the other conventional flash memory, described above.
As such, it is desirable to address one or more of the above issues.